Automatic circuit generation
process and apparatus

ABSTRACT

APPARATUS AND METHOD FOR AUTOMATICALLY GENERATING A TOPOLOGY FOR A LOGIC CIRCUIT TO BE EMBODIED IN A SEMICONDUCTOR WAFER. FIXED DATA, DESIGNER ORGINATED DATA AND CONTROL DATA ARE GENERATED AS AN INPUT TO A COMPUTER. THE FIXED DATA PROVIDES ELECTRICAL, AND TOPOLOGICAL QUALITIES OF EACH LOGICAL ELEMENT IN THE LOGIC CIRCUIT TO BE EMBODIED IN THE SEMICONDUCTOR WAFER. THE DESIGNER ORIGINATED DATA PROVIDES LOCATION IN AN ORDERED GRID LAYOUT. THE CONTROL DATA DESCRIBES (1) COMBINATIONS OF LOGICAL ELEMENTS IN THE LOGIC CIRCUIT BY TYPE OF COMBINATION, START AND END IN THE GRID ARRAY DESCRIPTIVE OF THE SEMICONDUCTOR WAFER AND (2) ELECTRICALLY COMMON COMBINATIONS. A PROGRAM EMPLOYS THE FIXED, DESIGNER ORIGINATED AND CONTROL DATA TO GENERATE COORDINATE DATA FOR EACH LOGICAL ELEMENT IN THE GRID ARRAY AS AN INPUT TO A GRAPHICAL PROCESSOR WHICH TRANSLATES THE COORDINATES INTO A TOPOLOGICAL PATTERN DESCRIPTIVE OF THE LOGIC CIRCUIT TO BE EMBODIED IN THE SEMICONDUCTOR WAFER.

Ulhfl l or UNIETED STATES li- T AND TRADEEKARL @FFIQE Published at therequest of the applicanc or owner in accordance with the Notice of Dec.16, 1869, 869 0.6 687. The abstracts of Defensive Publicationapplications are iclenilfiecl by all inctly numbered series and arearranged chronolo; cally. The heacllng of each abstract indicates thenumber of I lclucling claims anrl sheets of drawings coneeined in theapplication as originally filed. 'lh files of these a to the public forinspection and reproduckion may be purchased for 30 cents a sheet.

Defensive Publication applications have not been examiner to the meritsof alleged invention. The Parent and Trademark Oifice makes no assertionas to the novelty of the disclosed subject matter.

PUBLISH D NGVEMBER 4-, 1975 9&0 ll

Film n5 11m" STORAGE J5 msmonm. was 3 i DNA I lleuwll Apparatus andmethod for automatically generating a topology for a logic circuit to heembodied in a semiconductor wafer. Fixed data, designer origioatcd dataan control data are generated as an input to a computer. The fixed dataprovides electrical, and topological qualities of each logical elcmcntin the logic circuit to be omborlicd in the semiconductor Wafer. Thedesigner originaled data provides location in an ordered grid layout."he control data c cscrilacs (l) combinations of logical elements in thelogic circuit by type of combination, start and end in the grid arraydescriptive of tho semiconductor wafer and (2) electrically commoncombinations. A program employs Lhc fixed, designer originated andcontrol data to generaie coordinate data for each logical element in thegrid array as an input to a graphical processor which translates thecoordinates into a topological pattern dcscrictivc of the logic circuitto be embodied in the semiconductor Wafer.

PROCESS AND APPARATUS Original Filed April 17, 1974 T I G. E. BRECHLINGet a1. AUTOMATIC CIRCUIT GENERATION Sheet 1 of 10 FIGJ SEE FIG.I2 F

STORAGE MEANS GENERAL PURPOSE COMPUTER RAIIIIAI DATA FOR I 92 MmFOPOLTIGTCTTL I DATA FOR LL AEJE E I FIG.3

INSTRUCTIONS I J TABLE 111 RAILS WLR SEGMENTTSI 11 TABLE 05v. LOCATIONx=1 CHANTC) -0 FIG 5 NOV. 4, 1975 G. E. BRECHLING et a1. T940,020

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April17, 1974 Sheet 2 of 10 ABCDEFGHLJKLM I3 CHANNELS 2 3 4 5 6 STARTINGENDING No. OF FET'S GROUP START GROUP END RAIL No. RAIL No. 4 IN GROUPNET No. NET No.

I I I 2 3 I 2 0= SERIES I= PARALLEL 2=ALT. SERIES 3=DIFFUSION SUB-GROUPINPUTS |N3TR TALE 1 A,B,C i=1' 1 1 2 3 1 2 3 EF 3 I 5 e 2 3 4 4 H 4 0 3e 2 2 4 5 1M 5 2 3 4 3 2 s 6 L 6 0 5 e 1 5 4 IJA FIG.7C

NOV. 4, 1975 G. E. BRECHLING et a1. T940,02O

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April17, 1974 Sheet 3 0f 10 F|G.6A

RAIL 6 I05 RAIL 5 START Y COORD. RAIL WIDTH 79 (GRID UNITS) (GRIDUNITS)RAIL 4 I 7 8 5 2 29 I2 3 3 41 I2 2 RAIL 3 41 4 62 I2 RAIL 2 5 79 I2 29 6I05 8 I5 7 RAIL I H658 x (GRID UNITS) x x XGX d a y IDE PENINGMETALLIZATION F ox 0 A '-DIFFUSION I I i CHANNEL I I LENGTH IVADIFFUSION CHANNEL WIDTH FIG.6C

X METAL DIFFUSION OVERLAP (4 GRID UNITS) X D|FFUSION /OXIDE OVERLAP (4GRID UNITS) X 0XIDE /DIFFUSION OVERLAP I I GRID UNIT) X y DIFFUSIONMETAL DVERLAP I O GRID UNIT) I X DIFFUSION WIDTH (8 GRID UNITS) NOV. 4,1975 G. E. BRECHLING et a1. T940,02O

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Origin Filed Apn'l17, 1974 Sheet 5 Of 10 I00 IIs ENTER cIRcIIIT GEN. I'

INSTRUCTIONS YSTART IN TABLE II ACCESS wLRs FROM I02 I x= Xy CTR 118DATA BASE STORED ACCESS TABLET FOR IN TABLET BEvIcE PARAMETERS ACCESSDEVICE FORM sTART SEGMENT 120 COORDINATES LOCATIONS FROM DATA CHECKINTERSECTION sToRE IN TABLET ORDER DEVICES BY 106 ASCENDING I;cooRBINATE SEPARATE BY Y COORDINATE ASSIGN sTART SEGMENT COORDINATES ToNET TABLE 108 T I 0 f T ACCIiiSG: ITiArB1LE II 11O INTERPRETINSTRUGTIONI YZYH FORM END SEGMENT RAIL YES 152 ASSIGN END SEGMENT T0NET TABLE NOV. 4, 1975 G. E. BRECHLING et a1. T940,020

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April17, 1974 Sheet 6 of 10 YES ; 219 A TNTT. T (Y,X) FORM COORD. Y=STARTRAIL-1 VERTICAL DIFFUSION ExTENsToN 204 Y=Y+1 1 x cTR =x CTR+1 TABLE FORDEVICE PARAMETERS T 206 FORM sTART ASSIGN LAST SEGMENT GENERATED T0 NETTABLE ASSIGN SOURCE sTART SEGMENT To NET TABLE 214 Y=Y+1 J F|G.|2B FORMEND SEGMENT CHECK 1 NTERSECTION LAsT DEVICE TN NOV. 4, 1975 G. E.BRECHLING et a1. T940,02O

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April17, 1974 Sheet 7 of 10 320 FORM DIFF. COORD.

BETWEEN RAILS CHECK 1 AND 1+1 LOCATED INTERSECTTON VERTICALLY ABovE LASTDEVICE SUBGROUP ,304 306 Y=STARTRAIL+1 Y STARTRAlL-1 k=0 k=1 =0 1 =0 k=308 y FW I FORM 1 I x CTR =X CTR+1 1 TABLE I INTERSECTION ASSIGN STARTSEGMENT T0 NET TABLE NOV. 4, 1975 G. E. BRECHLING et a1. T94D,O2O

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April17, 1974 Sheet 8 of 10 ZZ mm II II II COO N =N +I ADDRESS END I 404SEGMENTS IN X=X+I NEW NET TABLE ACCESS I (N ,N3,X)

FOR END SEGMENT FORM SINGLE QHAPE CONNECT T0 END SEGMENT x IF ANY IX=X+I ACCESS J I (NE ,N3 ,x)

ADDRESS START I 409 SEGMENTS IN FORM 1 SAME NET TABLE SINGLE SHAPE X=X+I414 ACCESS I IN ,N ,XI FOR START 4T8 STORE STORE STORE X START SHAPE XSTART SHAPE X START SHAPE IN "UNDER SPAN" IN "OVER SPAN" IN IN SPANTABLE TABLE TABLE NOV. 4, 1975 G. E. BRECHLING et a1. T940,02O

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April17, 1974 Sheet 9 of 10 FIG. I2E

SHAPES T N OVERSPAN ACCESS HTCHEST ACCESS LOWEST 456 x COORO. SHAPExCOORO. SHAPE CONNECT TO CONNECT TO FIRST END SHAPE LAST END SHAPE CHECKCHECK ACCESS NEXT ACCESS NEXT LOWEST HTCHEST START SHAPE START SHAPE ACONNECT CONNECT T0 HIGHER TO LOWER 440 START SHAPE, START SHAPE,

IF ANY IF ANY ACCESS IN SPAN SHAPES OBTAIN NON -NET 1 446 SEGMENT,COORDINATE STORE OUTPUT Nov. 4, 1975 G. E. BRECHLING et al. T940,020

AUTOMATIC CIRCUIT GENERATION PROCESS AND APPARATUS Original Filed April17, 1974 Sheet 10 of 10 m. fi

